View LC865508A_2095329.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

91400 rm (im) tw-1/19 ver.1.02 12296 preliminary overview the lc865520a/16a/12a/08a/04a microcontrollers are 8-bit single chip microcontrollers with the following one-chip functional blocks: - cpu : operable at a minimum bus cycle time of 0.5 s (microsecond) - on-chip rom maximum capacity : 20k bytes - on-chip ram capacity : 512 bytes (lc865520a/16a/12a/08a/04a) - 16-bit timer /counter (or two 8-bit timers) - 16-bit timer /pwm (or two 8-bit timers) - 8-channel 8-bit ad converter - two 8-bit synchronous serial-interface circuits - 13-source 10-vectored interrupt system80 all of the above functions are fabricated on a single chip. features (1) read-only memory (rom) : lc865520a 20480 8 bits : lc865516a 16384 8 bits : lc865512a 12288 8 bits : LC865508A 8192 8 bits : lc865504a 4096 8 bits (2) random access memory (ram) : lc865520a/16a/12a/08a/04a 512 8 bits (3) bus cycle time/instruction cycle time the lc865520a/16a/12a/08a/04a are constructed to read rom twice within one instruction cycle. it has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcomputers (lc66000 series). bus cycle time indicates the speed to read rom. bus cycle time cycle time clock divider system clock oscillation oscillation frequency voltage 0.5 s 1 s 1/1 ceramic resonator oscillation 6mhz 4.5v to 6.0v 2 s 4 s 1/2 ceramic resonator oscillation 3mhz 2.5v to 6.0v 7.5 s 15 s 1/2 rc resonator oscillation 800khz 2.5v to 6.0v 183 s 366 s 1/2 crystal oscillation 32.768khz 2.5v to 6.0v 8-bit single chip microcontroller with on-chip 20/16/12/08/04k-byte rom and 512-byte ram lc865520a/16a/12a/08a/04a ordering number : enn*6697 cmos ic
lc865520a/16a/12a/08a/04a 2/19 (4) ports - input/output ports : 3 ports (16 terminals : port 1,7,8) input/output programmable in a bit - maximum 15v withstand input/output port : 2 ports (15 terminals) input/output port programmable in nibble units : 1 port (8 terminals : port 0) (when the n-channel open drain output is selected, the data in a bit can be inputted.) input/output port programmable in a bit : 1 port (7 terminals : port 3) - input ports : 2 ports (6 terminals : port 7,8) (5) ad converter - 8-channel 8-bit ad converter (6) serial-interface - 1 channel 16-bit serial-interface (8-bit transmission available by program) - 1 channel 8-bit serial-interface lsb first/msb first function available - internal 8-bit baud-rate generator in common with two serial-interface circuits (7) timer - timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with programmable prescaler + 8-bit counter mode 2 : 16-bit timer with programmable prescaler mode 3 : 16-bit counter the resolution of timer is t cyc. ( t cyc: cycle time) - timer 1 16-bit timer/pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable-bit pwm (9-16bits) in mode 0 and mode 1,the resolution of timer and pwm is t cyc. in mode 2 and mode 3,the resolution of timer and pwm selectable: t cyc or 1/2 t cyc by program. - base timer every 500ms overflow system for a clock application (using 32.768khz crystal oscillation for base timer clock) every 976 s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768khz crystal oscillation for base timer clock) the base timer clock selectable; 32.768khz crystal oscillation, system clock, and programmable prescaler output of timer 0 (8) buzzer output - the buzzer sound frequency selectable; 4khz, 2khz (using 32.768khz crystal oscillation for base timer clock) (9) remote-control receiver circuit (shares with p73/int3/t0in terminal) - noise rejection function (the time constant of noize rejection filter: 1t cyc/16 t cyc/64 t cyc ) (t cyc: instruction cycle time ) - switch polarity function (10) watchdog timer - the watchdog timer is taken on rc outside - watchdog timer operation selectable: interrupt system, system reset
lc865520a/16a/12a/08a/04a 3/19 (11) interrupt system - 13-source 10-vectored interrupts : 1. external interrupt int0 (include watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8-bit) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8-bit) 6. timer t1l, timer t1h 7. serial-interface sio0 8. serial-interface sio1 9. ad converter 10. port 0 - built-in interrupt priority control register microcomputer allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. it can specify a low level or a high level interrupt priority from int2/t0l through port 0 (i.e. the above interrupt number from three through ten). it can also specify a low level or the highest level interrupt priority to int0 and int1. (12) subroutine stack levels - 128 levels (max.): stack area included in ram area (13) multiplication and division 16-bit 8-bit (7 instruction cycle times) 16-bit / 8-bit (7 instruction cycle times) (14) 3 oscillation circuits - on-chip rc oscillation circuit using for the system clock. - on-chip cr oscillation circuit using for the system clock. - on-chip crystal oscillation circuit using for the system clock and for time-base clock. (15) standby function - halt mode function the halt mode is used to reduce power dissipation. in this operation mode, program execution is stopped. this operation mode can be released by interrupt request signals or the initial system reset request signal. - hold mode function the hold mode is used to freeze all the oscillations; rc (internal), cr and crystal oscillations. this mode can be released by the following operations. reset terminal ( res ) set to low level p70/int0/t0in, p71/int1/t0in terminals set to assigned level (programmable) port 0 terminal/terminals set to low level (programmable) (16) factory shipment dip42s, qfp48e delivery form (17) development support tools evaluation (eva) chip : lc866096 eprom version : lc86e5420 one time version : lc86p5420 emulator : eva-86000 + ecb867100 (evaluation chip board) + pod865400 (pod) notice for use 1. follow the under table. frequency range of the system clock voltage range clock divider note 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 6mhz 4.5v to 6.0v 1/1,1/2 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 1.5mhz 1/1,1/2 1.5mhz to 3mhz 2.5v to 6.0v 1/2 can not use 1/1 divider 4.5v to 6.0v 1/1,1/2 internal rc oscillation 2.5v to 6.0v 1/2 can not use 1/1 divider
lc865520a/16a/12a/08a/04a 4/19 pin assignment package dimension (unit : mm) 3025b sanyo : dip-42s(600mil) package dimension (unit : mm) 3156 sanyo : qip-48e *nc pin must not connect to anything.
lc865520a/16a/12a/08a/04a 5/19 system block diagram port 1 port 0 stack pointer ram rar psw alu c register watch dog timer port 7 sio1 sio0 acc bus interface base timer pc rom pla ir cr x?tal rc clock generator interrupt control stand-by control b register port 8 timer 0 port 3 int0-3 noise filter adc timer 1
lc865520a/16a/12a/08a/04a 6/19 pin description pin name i/o function description option vss - power pin (-) - vdd - power pin (+) - port0 p00 to p07 i/o 8-bit input/output port input for port 0 interrupt input/output in nibble units input for hold release 15v withstand at n-channel open drain output pull-up resistor : provided/not provided (each nibble) output form : cmos/n-channel open drain (each bit) port1 p10 to p17 i/o 8-bit input/output port input/output can be specified in a bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer 1 output (pwm0 output) output form : cmos/n-channel open drain (each bit) port3 p30 to p36 i/o 7-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output pull-up resistor : provided/not provided (each bit) output form : cmos/n-channel open drain (each bit) 4-bit input/output port input/output in bit unit 2-bit input port other pin functions p70 : int0 input/hold release/n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input p74 : 32.768khz crystal oscillation terminal xt1 p75 : 32.768khz crystal oscillation terminal xt2 interrupt received forms, the vector addresses rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h port7 p70 to p73 p74 , p75 i/o i int3 enable enable enable disable disable 1bh continue.
lc865520a/16a/12a/08a/04a 7/19 pin name i/o function description option port8 p80 to 83 p84 to 87 i i/o 4-bit input port input/output in bit unit 4-bit input/output port other function ad input port (8port pins) - res i reset pin - xt1/ p74 i input pin for 32.768khz crystal oscillation other function xt1 : input port p74 in case of non use, connect to vdd. - xt2/p75 o output pin for 32.768khz crystal oscillation other function xt2 : input port p75 in case of non use, connect to vdd at using as port or unconnect at using as oscillation. - cf1 i input pin for the ceramic resonator oscillation - cf2 o output pin for the ceramic resonator oscillation - * all of port options (except pull-up resistor of port 0) can be specified in bit unit. *a state of pins at reset pin name input/output mode a state of pull-up resistor specified at pull-up option port 0 input fixed pull-up resistor off ports 1,3 input programmable pull-up resistor off
lc865520a/16a/12a/08a/04a 8/19 1. absolute maximum ratings at vss=0v and ta=25 c ratings parameter symbol pins conditions v dd [v] min. typ. max. unit supply voltage vddmax vdd vdd -0.3 +7.0 input voltage vi(1) ports 74 ,75 ports 80,81,82,83 res -0.3 vdd+0.3 vio(1) port 1 ports 70,71,72,73 ports 84,85,86,87 ports 0, 3 at cmos output option -0.3 vdd+0.3 input/output voltage vio(2) ports 0, 3 at n-ch open drain output option -0.3 15 v peak output current ioph ports 0, 1, 3 ports 71,72,73 ports 84,85,86,87 cmos output at each pins -10 ioah(1) ports 0, 1 the total of all pins -30 ioah(2) port 3 the total of all pins -15 high level output current total output current ioah(3) ports 71,72,73 ports 84,85,86,87 the total of all pins -10 iopl(1) ports 0, 1, 3 at each pins 20 peak output current iopl(2) ports 70,71,72,73 ports 84,85,86,87 at each pins 15 ioal(1) ports 0,1,70 the total of all pins 60 ioal(2) port 3 the total of all pins 40 low level output current total output current ioal(3) ports 71,72,73 ports 84,85,86,87 the total of all pins 20 ma pdmax(1) dip42s ta=-30 to+70 c 630 maximum power dissipation pdmax(2) qfp48e ta=-30 to+70 c 390 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
lc865520a/16a/12a/08a/04a 9/19 2. recommended operating range at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s t cyc t cyc 400 s 4.5 6.0 operating supply voltage vdd(2) vdd 3.9 s t cyc t cyc 400 s 2.5 6.0 hold voltage vhd vdd rams and the registers hold voltage at hold mode. 2.0 6.0 vih(1) port 0 at cmos output output disable 2.5 to 6.0 0.33vdd +1.0 vdd 4.0 to 6.0 0.75vdd 13.5 vih(2) port 0 at n-ch open drain output output disable 2.5 to 4.0 0.8vdd 13.5 vih(3) port 1 ports 72,73 port 3 at cmos output output disable 2.5 to 6.0 0.75vdd vdd 4.5 to 6.0 0.75vdd 13.5 vih(4) port 3 at n-ch open drain output output disable 2.5 to 4.0 0.8vdd 13.5 vih(5) port 70 port input/interrupt port 71 res output disable 2.5 to 6.0 0.75vdd vdd input high voltage vih(6) port 70 watchdog timer output disable 2.5 to 6.0 0.9vdd vdd vih(7) port 8 ports 74 ,75 output disable using as port 2.5 to 6.0 0.75vdd vdd vil(1) port 0 at cmos output option output disable 2.5 to 6.0 vss 0.2vdd vil(2) port 0 at n-ch open drain output output disable 2.5 to 6.0 vss 0.25vdd vil(3) ports 1,3 ports 72,73 output disable 2.5 to 6.0 vss 0.25vdd vil(4) port 70 port input/interrupt port 71 res output disable 2.5 to 6.0 vss 0.25vdd vil(5) port 70 watchdog timer output disable 2.5 to 6.0 vss 0.8vdd -1.0 input low voltage vil(6) port 8 ports 74 ,75 output disable using as port 2.5 to 6.0 vss 0.25vdd v 4.5 to 6.0 0.98 400 operation cycle time t cyc 2.5 to 6.0 3.9 400 s fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5 to 6.0 5.88 6 6.12 fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 2.5 to 6.0 2.94 3 3.06 fmrc rc oscillation 2.5 to 6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 2.5 to 6.0 32.768 khz continue.
lc865520a/16a/12a/08a/04a 10/19 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5 to 6.0 4.5 to 6.0 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 2.5 to 6.0 ms 4.5 to 6.0 oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 2.5 to 6.0 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc865520a/16a/12a/08a/04a 11/19 3. electrical characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0,3 at open drain output output disable vin=13.5v (including off-leakage current of the output tr.) 2.5 to 6.0 5 iih(2) port 0 without pull-up mos tr. ports 1,3 ports 70,71,72,73 port 8 output disable pull-up mos tr. off. vin=vdd (including off-leakage current of the output tr.) 2.5 to 6.0 1 iih(3) res vin=vdd 2.5 to 6.0 1 input high current iih(4) ports 74 ,75 vin=vdd using as port 2.5 to 6.0 1 iil(1) ports 1,3 port 0 without pull-up mos tr. ports 70,71,72,73 port 8 output disable pull-up mos tr. off. vin=vss (including off-leakage current of the output tr.) 2.5 to 6.0 -1 iil(2) res vin=vss 2.5 to 6.0 -1 input low current iil(3) ports 74 ,75 vin=vss using as port 2.5 to 6.0 -1 a voh(1) ioh=-1.0ma 4.5 to 6.0 vdd-1 output high voltage voh(2) ports 0,1,3 of cmos output ports 71,72,73 ports 84,85,86,87 ioh=-0.1ma 2.5 to 6.0 vdd-0.5 vol(1) iol=10ma 4.5 to 6.0 1.5 vol(2) iol=1.6ma 4.5 to 6.0 0.4 vol(3) ports 0,1,3 iol=1.0ma the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 0.4 vol(4) iol=1.6ma 4.5 to 6.0 0.4 v vol(5) ports 71,72,73 ports 84,85,86,87 iol=0.5ma the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 0.4 vol(6) iol=1ma 4.5 to 6.0 0.4 output low voltage vol(7) port 70 iol=0.5ma the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 0.4 4.5 to 6.0 15 40 70 pull-up mos tr. resistor rpu ports 0,1,3 ports 70,71,72,73 ports 84,85,86,87 voh=0.9vdd 2.5 to 4.5 25 70 150 k ? hysteresis voltage vhis port 1 ports 70,71,72,73 res output disable 2.5 to 6.0 0.1vdd v pin capacitance cp all pins f=1mhz vin=vss for all unmeasured terminals. ta=25 c 2.5 to 6.0 10 pf
lc865520a/16a/12a/08a/04a 12/19 4. serial input/output characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) sck0,sck1 refer to figure 5 2.5 to 6.0 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2t ckcy serial clock output clock high level pulse width t ckh (2) sck0,sck1 use pull-up resistor (1k ? ) in the open drain output. refer to figure 5 2.5 to 6.0 1/2t ckcy t cyc 4.5 to 6.0 0.1 data set-up time t ick 2.5 to 6.0 0.4 4.5 to 6.0 0.1 serial input data hold time t cki si0,si1 sb0,sb1 data set-up to sck0,1 data hold from sck0,1 refer to figure 5 2.5 to 6.0 0.4 4.5 to 6.0 7/12 t cyc +0.2 output delay time (external clock using for serial transfer clock) t cko(1) 2.5 to 6.0 7/12 t cyc +1 4.5 to 6.0 1/3 t cyc +0.2 serial output output delay time (internal clock using for serial transfer clock) t cko(2) so0,so1 sb0,sb1 use pull-up resistor (1k ? ) in the open drain output. data hold from sck0,1 refer to figure 5 2.5 to 6.0 1/3 t cyc +1 s
lc865520a/16a/12a/08a/04a 13/19 5. pulse input conditions at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 2.5 to 6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock selected to 1/1.) interrupt acceptable timer0-countable 2.5 to 6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock selected to 1/16.) interrupt acceptable timer0-countable 2.5 to 6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock selected to 1/64.) interrupt acceptable timer0-countable 2.5 to 6.0 128 t cyc high/low level pulse width tpil(5) res reset acceptable 2.5 to 6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5 to 6.0 8 bit absolute precision (note 2) et 4.5 to 6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5 to 6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5 to 6.0 vss vdd v iainh vain=vdd 4.5 to 6.0 1 analog port input current iainl an0 to an7 vain=vss 4.5 to 6.0 -1 a (note 2) absolute precision excepts the quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc865520a/16a/12a/08a/04a 14/19 7. current dissipation characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5 to 6.0 7 18 iddop(2) 4.5 to 6.0 3 7 iddop(3) fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 1.5 5 iddop(4) 4.5 to 6.0 0.7 3 iddop(5) fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5 to 4.5 0.4 2.5 ma iddop(6) 4.5 to 6.0 35 130 current dissipation during basic operation (note 4) iddop(7) vdd fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : 32.768khz internal rc oscillation stops 1/2 divided 2.5 to 4.5 15 70 continue.
lc865520a/16a/12a/08a/04a 15/19 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5 to 6.0 4 9 iddhalt(2) 4.5 to 6.0 2.2 5 iddhalt(3) halt mode fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 0.8 3 ma iddhalt(4) 4.5 to 6.0 400 1600 iddhalt(5) halt mode fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5 to 4.5 200 1300 iddhalt(6) 4.5 to 6.0 25 100 current dissipation in halt mode (note 4) iddhalt(7) vdd halt mode fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 8 55 iddhold(1) 4.5 to 6.0 0.05 30 current dissipation in hold mode (note 4) iddhold(2) vdd hold mode 2.5 to 4.5 0.02 20 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
lc865520a/16a/12a/08a/04a 16/19 table 1. ceramic resonator oscillation recommended constant (main-clock) oscillation type maker oscillator c1 c2 csa6.00mg murata cst6.00mgw kbr-6.0msa pbrc6.00a (chip type) kbr-6.0mks 6mhz ceramic resonator oscillation kyocera pbrc6.00b (chip type) csa3.00mg murata cst3.00mgw 3mhz ceramic resonator oscillation kyocera kbr-3.0ms * both c1 and c2 must be use k rank (10%) and sl characteristics. table 2. crystal oscillation guaranteed constant (sub-clock) oscillation type maker oscillator c3 c4 rd 32.768khz crystal oscillation * both c3 and c4 must be use j rank (5%) and ch characteristics. (not in need of high precision, use k rank (10%) and sl characteristics.) (notes) please place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible p attern length since the circuit pattern affects the oscillation frequency. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 main-clock circuit figure 2 sub-clock circuit ceramic resonator oscillation crystal oscillation c1 c2 cf cf2 cf1 c3 rd c4 x?tal xt2 xt1
lc865520a/16a/12a/08a/04a 17/19 figure 3 oscillation stable time operation mode xt1, xt2 cf1, cf2 internal rc resonator oscillation res instruction execution mode instruction execution mode i nstruct i on execution mode ocr6=1 reset valid unfixed tssxtal tmscf reset time vdd vdd limit 0v power supply operation mode xt1, xt2 cf1, cf2 internal rc resonator oscillation hold release signal hold tssxtal tmscf
lc865520a/16a/12a/08a/04a 18/19 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of c res , r res that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. c res vdd r res res so0, so1 sb0, sb1 si0 si1 sck0 sck1 50pf 1k ? vdd tcko tcki tick tckh tckl tckcy 0.5vdd tpih tpil
lc865520a/16a/12a/08a/04a 19/19 memo: ps

▲Up To Search▲

Price & Availability of LC865508A

	To Download LC865508A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .